The Accelerated Graphics Port (AGP) is a high performance component interface designed specifically for 3-D graphical display applications in personal computers. Essentially, the AGP provides performance enhancement to the PCI bus by allowing graphics accelerators to directly access main system memory. In order to optimize performance, the AGP also provides deeply pipelined memory read and write operations such that main system memory access latency is hidden.
Specifically, AGP transactions are run in a split transaction fashion where the requests for data transfer (or access requests) are "disconnected" from the data transfers. That is, in operation, an AGP compliant device initiates an AGP transaction with an access request. Then, memory controller or core logic responds to the access request by directing the corresponding data transfer at a later time. The fact that the access requests are separated from the data transfers allows AGP compliant devices to issue several access requests in a pipelined fashion while waiting for the data transfers to occur. This feature significantly increases the performance of AGP compliant devices.
In addition to providing pipelined memory read and write operations, the AGP supports two levels of access priorities: high-priority access and low-priority access. Generally, the memory controller subsystem processes high-priority access requests before low-priority access requests. Access requests are further classified into read access requests and write access requests, which, respectively, control read and write operations of the memory controller subsystem. Thus, in an AGP system, access requests may be classified into 4 different request types: high-priority read, high-priority write and their respective low-priority counterparts. An AGP system may also support other access request types, such as long read and long write operations, as well as flushing operations. Further, the AGP also supports multiple request-issuing agents and multiple "slave" devices.
In order to support these different request types, it is desirable to implement a request pipeline which is capable of separating different types of requests into different subqueues such that each request type may be dealt with separately in the slave device(s). One prior art implementation of such a request pipeline is illustrated in FIG. 1. As shown, the prior art access request pipeline 100 comprises a logic circuit 102 and a plurality of subqueues 104 corresponding to different levels of priorities and/or request types. The request issuing agent or "master" 10 is coupled to provide a stream of requests to logic circuit 102. Logic circuit 102 then determines a priority and/or request type of each request, and places the requests into the corresponding subqueues 104. For instance, a high-priority read access request will be placed in the high-priority read subqueue. Similarly, access requests of other types are placed into other subqueues corresponding to their request types. Typically, each subqueue is implemented by a simple first-in-first-out memory unit (FIFO). That is, each access request will be output in the order in which they are stored in the subqueue.
Although the prior art access request pipeline 100 is useful for its intended purposes, one drawback is that it requires a large number of storage elements. For instance, if a system supports W-bit access requests, N request types, and a maximum number of D outstanding access requests, a minimum number of N*D*W storage elements are required to implement the request pipeline. However, at any one instance, a maximum number of D*W storage elements are used. Thus, a significant number of storage elements are not used at any one time, unnecessarily increasing manufacturing costs and wasting valuable die area of integrated circuits implemented with the prior art access request pipeline 100.
Thus, what is needed is an apparatus for and method of arbitrating a stream of digital data over multiple outputs. What is further needed is an apparatus for and method of arbitrating a stream of requests over multiple outputs using a minimum number of storage elements. What is yet further needed is an apparatus for and method of implementing an access request pipeline for accelerated graphics port (AGP) with a minimum number of storage elements.